1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor-chip-layered-type semiconductor device.
2. Description of the Related Art
As portable equipment increases its functions and decreases its size, the demand for SiP (System in Packages), where a plurality of semiconductor chips and passive elements are packaged at high density, is increasing. One type of SiP package structure is an MCP (Multi Chip Package) type, where a plurality of semiconductor chips are vertically stacked or horizontally disposed in an ordinary package having a standard external shape. Another type of SiP package structure is a module type, where a plurality of semiconductor chips and passive elements are mounted on an interposer.
Still another type of SiP package structure is a wafer-level type, which is characterized by a small and slim SiP structure and by a fact that a semiconductor device is fabricated at the wafer level. A typical example of this type of semiconductor device has a plurality of semiconductor chips mounted on a support substrate, an organic insulation layer covering the semiconductor chips, and interconnections formed on the organic insulation layer. Vias for connecting the pads of semiconductor chips with the interconnections are repeatedly formed and layered. Further, another vias are provided for electrically connecting the semiconductor chips in upper and lower layers (that is, semiconductor chips in a certain layer are connected to another semiconductor chips in its upper or lower layer by these vias). In other words, the above-described semiconductor device has a multilayer structure, where semiconductor chips from higher layers (or a top layer) to lower layers (or a bottom layer) are electrically connected.
Japanese Patent Application Laid-Open (Kokai) No. 2001-196525 discloses interconnection patterns that are formed on a support substrate. The interconnection patterns are electrically connected to semiconductor chips via bumps (in other words, flip chip packaging), so that smaller and lighter devices than prior art can be implemented.
Japanese Patent Application Laid-Open (Kokai) No. 2001-135787 discloses a method for judging the quality of bump connection accurately and quickly when flip chip packaging is performed for semiconductor devices having a chip-on-chip structure.
However, all characteristics of semiconductor chips cannot be confirmed merely by probing before packaging. In some cases a defective semiconductor chip is discovered only after the packaging thereof on an interconnection pattern. Therefore it is inevitable for defective semiconductor chips to be mixed in a device. When a defective semiconductor chip is found after the packaging, that device should be discarded even though the device contains non-defective semiconductor chips. In such a case, non-defective semiconductor chips are wasted. If semiconductor chips are made by a process of which stability of the yield is insufficient, then yield at the SiP level drops, and non-defective semiconductor chips are wasted.